As is well known in the field of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required for the implementation of the desired function. Of course, the geometries and sizes of the active components such as the gate electrode in metal-oxide-semiconductor (MOS) technology, and as diffused regions such as MOS source and drain regions and bipolar emitters and base regions, are important factors in defining the chip area for a given integrated circuit. These geometries and sizes are often dependent upon the photolithographic resolution available for the particular manufacturing facility.
Another important factor in the chip area required for a given integrated circuit is the isolation technology, as sufficient electrical isolation must be provided between active circuit elements so that leakage therebetween does not cause functional or specification failure. The importance of isolation is particularly great for circuits such as static random access memories (SRAMs), particularly in recent years where maintenance of the stored data by extremely low levels of standby current has become highly desirable. Such low standby currents require excellent isolation, as the presence of leakage between active regions in the memory array will greatly increase the standby current drawn. The increasingly stringent standby current specifications, together with the demand for smaller memory cells in denser memory arrays, places significant pressure on the isolation technology in SRAM devices, as well as in other modern integrated circuits.
A well-known and widely-used isolation technique is the local oxidation of silicon, commonly referred to as LOCOS. In LOCOS, an oxidation barrier (generally silicon nitride) is placed over the locations of the surface of the chip into which the active devices are to be formed (i.e., the active regions). The wafer is then placed in an oxidizing environment, generally in steam at a high temperature such as 1100.degree. C. The portions of the wafer surface not covered by the oxidation barrier oxidize to form thermal silicon dioxide thereat, with oxidation masked from the active regions by the oxidation barrier. LOCOS field oxide is generally formed to a sufficient thickness that a conductor placed thereover will not invert the channel thereunder, when biased to the maximum circuit voltage.
While LOCOS isolation is widely-used in the industry, it is subject to certain well-known limitations. A first significant limitation of LOCOS is encroachment of the oxide into the active regions, due to oxidation of silicon under the edges of the nitride mask. The expected distance of such encroachment must be considered in the layout of the integrated circuit; as such, the chip area is expanded as a result of the encroachment. Of course, the encroachment may be reduced by reducing the field oxide thickness, but at a cost of reduction of the threshold voltage of the parasitic field oxide transistor, and thus reduction of the isolation provided.
In addition, conventional LOCOS isolation adds topography to the integrated circuit surface. This is because the silicon dioxide must necessarily occupy a greater volume than that of the silicon prior to its oxidation, due to the reaction of the oxygen therewith. As a result, the surface of conventional LOCOS field oxide is above the surface of the active regions, with approximately half of the oxide thickness being above the active region surface. This topography requires overlying conductors to cover steps at the edges of the field oxide which, as is well known, presents the potential for problems in etching the conductor layer (i.e., the presence of filaments) and in the reliability of the conductor layer. In addition, the depth of field for sub-micron photolithography can be exceeded by the topography of the wafer surface.
A more recent isolation technique uses trenches etched into the surface of the wafer at the isolation locations, which are subsequently filled with a thermal or deposited oxide. Such trench isolation can provide extremely thick isolation oxides which extend into the wafer surface with little or no encroachment, and which can have an upper surface which is relatively coplanar with adjacent active regions. An example of such trench isolation is described in U.S. Pat. No. 4,958,213, where a relatively deep trench is etched and subsequently filled with both deposited oxide and thermal oxide. It should be noted, however, that the etching of deep trenches is a relatively expensive process, and one which is quite difficult to perform while maintaining close geometries. In addition, it is well known that thermally formed silicon dioxide generally has higher integrity than deposited silicon dioxide; the formation of thermal oxide in trenches, however, causes stress in the silicon, due to the volume expansion of silicon dioxide from that of the silicon prior to its oxidation. As a result, trench isolation tends to rely on deposited oxide to a large degree.
By way of further background, U.S. Pat. No. 4,842,675 describes a method of forming thermal LOCOS field oxide in combination with trenches. According to this method, recesses are etched into the surface of the wafer at the desired isolation locations. A conformal layer of silicon nitride is deposited thereover, followed by deposition of a thicker layer of silicon oxide. The deposited silicon oxide is etched back to expose the silicon nitride at the bottom of the wider isolation locations, but not within the narrower isolation locations. The exposed nitride is etched away, the deposited silicon oxide is removed, and the exposed single crystal portions of the wafer are thermally oxidized in conventional LOCOS fashion. The remainder of the volume of the isolation locations are filled with deposited oxide, after the formation of the thermal oxide. It should be noted, however, that the availability of silicon for such oxidation is limited to that at the bottom surface of the wider recess. In addition, the process appears to be quite complex.
It is therefore an object of this invention to provide a method of forming an isolation structure having a surface which is substantially coplanar with the surface of the adjacent active regions.
It is a further object of this invention to provide such a method which utilizes thermal silicon dioxide as the isolation material.
It is a further object of this invention to provide such a method which utilizes relatively shallow trenches in the surface of the wafer.
It is a further object of this invention to provide such a method which substantially fills the isolation recesses with thermal silicon dioxide.
It is a further object of this invention to provide such a method which can be used for both wide and narrow isolation locations.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.